Voltage multiplier circuits are used in integrated circuits (ICs) to generate voltages that are greater than the IC supply voltage. A voltage multiplier circuit includes a charging circuit (e.g., a charge pump) and a feedback control circuit. The charging circuit charges a capacitive structure to generate an elevated output voltage, while the feedback control circuit monitors the elevated output voltage and enables or disables the charging circuit to regulate the output voltage. Because the elevated output voltage is greater than the supply voltage to the IC, the feedback control circuit must scale down the elevated output voltage so that it can be compared with a non-elevated reference voltage. Typically, the scaling down of the elevated output voltage is performed using a resistive divider.
FIG. 1 shows a circuit diagram of a conventional voltage multiplier circuit 100 for providing an elevated output voltage VPP to a load 120. Voltage multiplier circuit 100 includes a charge pump 110, a resistive divider 130, and a comparator 190. Charge pump 110 receives an input voltage VDD (i.e., an internal supply voltage of the IC in which voltage multiplier circuit 100 is implemented) at an input terminal IN, which charges up an internal capacitor (not shown) to generate an elevated output voltage VPP at an output terminal OUT. To regulate elevated output voltage VPP, resistive divider 130 generates a scaled down voltage VSCALE that is proportional to elevated output voltage VPP. Comparator 190 then compares scaled down voltage VSCALE to a predetermined reference voltage VREF to generate a charging enable signal CHARGE, which is fed to an enable terminal EN of charge pump 110 to control the charging operation of charge pump 110. Therefore, the relative values of scaled down voltage VSCALE and reference voltage VREF determine the behavior of charge pump 110.
To generate scaled down voltage VSCALE, resistive divider 130 includes a series of resistors 131-138 that are connected between output terminal OUT of charge pump 110 and ground. Scaled down voltage VSCALE is read from a tap point T within this series of resistors, and is therefore defined by the particular resistance values of resistors 131-138. For example, if resistors 131-138 all have the same resistance, then the voltage drop across each resistor is the same, and scaled down voltage VSCALE is equal to one eighth of elevated output voltage VPP. Reference voltage VREF would then be set equal to one eighth of a target output voltage VTAR (i.e., the elevated voltage required by load 120), in which case comparator 190 would assert charging enable signal CHARGE until scaled down voltage VSCALE rose to one eighth of target voltage VTAR. For example, for a target output voltage VTAR of 8V, reference voltage VREF would typically be set to 1.0V (i.e., 8V/8), in which case charging enable signal CHARGE would be asserted while scaled down voltage VSCALE was less than 1.0V, and charging enable signal CHARGE would be deasserted once scaled down voltage VSCALE reached 1.0V.
However, during a charging operation resistive divider 130 is not in a steady state condition, and so scaled down voltage VSCALE does not represent the actual level of elevated output voltage VPP during the charging operation. This is because a conventional resistive divider circuit such as resistive divider 130 typically experiences a voltage propagation lag across the individual resistors making up the divider circuit due to parasitic capacitances associated with the resistors (indicated by capacitances 141-148).
This voltage propagation lag is proportional to the resistance and parasitic capacitance values associated with the resistive divider. Unfortunately, resistive dividers are typically assigned large resistance values to minimize power loss through the circuit. The larger the resistance of the resistive divider, the smaller the parasitic current flow though the resistive divider, and the smaller the power consumption of that resistive divider. A resistive divider for a charge pump feedback control circuit generally has a resistance in the mega-ohm range, which results in microampere parasitic currents. To create such large resistances in an IC, large resistive elements are required, which in turn create large parasitic capacitances.
For example, FIG. 2 shows a layout diagram for a conventional resistive divider 200 for a voltage multiplier circuit (such as resistive divider 130 shown in FIG. 1). Resistive divider 200 includes a polysilicon resistor 230 formed on a dielectric layer 220 over an N-well 210. Polysilicon resistor 230 is connected between elevated output voltage VPP from a charge pump (not shown for clarity) and ground. Scaled down voltage VSCALE is read from a tap point T at an interior location of polysilicon resistor 230, and is therefore determined by the specific location of tap point T along the length of polysilicon resistor 230. The closer tap point T is to the grounded end of polysilicon resistor 230, the smaller scaled down voltage VSCALE becomes relative to elevated output voltage VPP.
Because n-well 210 cannot be left floating, N-well 210 is grounded via well contacts 241 and 242, which are formed on dielectric layer 211 but are connected to N-well 210 by a plurality of interconnects 243. Unfortunately, because N-well 210 and polysilicon resistor 230 are separated by a dielectric layer, the grounding of N-well 210 capacitively couples polysilicon resistor 230 to ground. Returning to FIG. 1, this capacitive coupling is indicated by capacitors 141-148. As noted above, this capacitive coupling is problematic because it creates a voltage propagation delay through resistive divider 130. The delay is proportional to a time constant RC defined by the following formula:RC=Rprev*Cprev  (1) where Rprev is the total resistance of the resistive divider between tap point T and the output terminal OUT of charge pump 110, and Cprev is the total parasitic capacitance associated with Rprev. For example, as depicted in FIG. 1, resistance Rprev would be defined by:Rprev=R131+R132+R133+R134+R135+R136+R137  (2) where R(xxx) represents the resistance of resistor xxx. Meanwhile, parasitic capacitance Cprev would be defined by:Cprev=C131+C132+C133+C134+C135+C136+C137  (3) where C(xxx) represents the capacitance of capacitor xxx.
Thus, because the resistance of resistive divider 130 is increased to minimize parasitic current loss through resistive divider 130, the parasitic capacitance associated with resistive divider 130 is increased, which in turn increases the voltage propagation delay through resistive divider 130. This propagation delay means that comparator 190 deasserts charging enable signal CHARGE at some point in time after elevated output voltage VPP has reached target output voltage VTAR. Because charge pump 110 continues to perform charging operations during this charging lag interval (i.e., during the time after elevated output voltage VPP has reached target output voltage VTAR but before scaled down voltage VSCALE has reached reference voltage VREF), elevated output voltage VPP can become significantly greater than target output voltage VTAR by the time charging enable signal CHARGE is deasserted. This overshoot of target output voltage VTAR by elevated output voltage VPP can result in damage to thin oxides and other structures within load 120. The problem is exacerbated by the fact that if load 120 does not have a high current draw, the only way for elevated output voltage VPP to be reduced is by current flow through the high resistance resistive divider 130, which has been expressly configured to minimize such parasitic current flow. Therefore, once overcharging has occurred, elevated output voltage VPP tends to remain in that overcharged state for a significant duration.
FIG. 3A shows a sample graph of elevated output voltage VPP versus time for a conventional voltage multiplier circuit (such as voltage multiplier circuit 100 shown in FIG. 1). FIGS. 3B and 3C show corresponding graphs of voltage VSCALE versus time and charging enable signal CHARGE versus time, respectively. When charging enable signal CHARGE is initially asserted (i.e., placed in the ON state) at time T0, elevated output voltage VPP begins rising as the charge pump in the voltage multiplier circuit begins charging. Consequently, voltage VSCALE also begins rising as elevated output voltage VPP increases the voltage across the resistive divider in the voltage multiplier circuit. However, as described above, the response of the resistive divider lags elevated output voltage VPP, so when elevated output voltage VPP reaches target voltage VTAR at time T1, scaled down voltage VSCALE is still at an interim voltage VINT that is less than reference voltage VREF. Therefore, even though elevated output voltage VPP has reached target voltage VTAR, the charge pump continues its charging operation until scaled down voltage VSCALE reaches reference voltage VREF at time T2 and charging enable signal CHARGE is deasserted (i.e., placed in the OFF state). However, by this time, output voltage VPP has risen to an overshoot voltage VOVR that is greater than target voltage VTAR, which can lead to IC damage and reliability problems. Note that elevated output voltage VPP decreases very slowly after charge pump operation has ceased (i.e., after time T2) due to the large resistances used in the resistive divider (as described above).
To overcome this overcharging problem, conventional voltage multiplier circuits are typically customized for specific load characteristics. For example, for a small capacitive load (i.e., a load that does not require substantial current flow), a charge pump having a relatively small capacitive structure can be operated at a relatively low charging frequency to minimize the chances of output voltage overshoot. However, such a voltage multiplier would not be suitable for loads requiring increased current flow. Such high-current loads would require a larger capacitive structure in the charge pump and a higher charging frequency to supply the higher current demands. But this type of “high capacity” voltage multiplier circuit could not be used with a small capacitive load, as the higher charging frequency would cause greater output voltage overshoot and the lack of current draw by the load would leave only the slow charge dissipation via the resistive divider. Thus, to minimize the effects of output voltage overshoot, conventional voltage multiplier circuits must be individually designed for each different load being serviced.
Accordingly, it is desirable to provide a voltage multiplier circuit that minimizes output voltage overshoot and can be used with a variety of output loads.